Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

Sensors
Freescale Semiconductor, Inc.

15

Interrupt flag is set on reaching the value stored in the Temperature target register. Additionally a window value provides ability 

to signal when the target is nearing from either above or below the value in the Temperature target register.

Note: When the window value is set to 0 then the interrupt will only be generated when reaching or crossing the target value.

The interrupt flag is set when the temperature value is within the window defined by the following formula:

Note: No interrupt is generated if the T_WND value is set to 0.

Interrupt flag is set if sequential Pressure/Altitude acquisitions exceed value stored in Pressure/Altitude window value register.

Interrupt flag is set if sequential Temperature acquisitions exceed the value stored in Pressure/Altitude window value register.

Interrupt flag is set when new data or a data overwrite event has occurred. PTOW and/or PTDR (DR_STATUS register) must 

be set for an interrupt to be generated.

Interrupt flag is set when either an overflow or watermark event has occurred. For more information please see 

.

Registers show the differences from the last Pressure/Altitude and Temperature samples.

Registers record the minimum and maximum Pressure/Altitude and Temperature. 

The registers embedded inside the device are accessed through an I

2

C serial interface.

There are two signals associated with the I

2

C bus: the Serial Clock Line (SCL) and the Serial Data line (SDA). The latter is a 

bidirectional line used for sending and receiving the data to/from the interface. External pull-up resistors connected to V

DD

 are 

expected for SDA and SCL. When the bus is free both the lines are high. The I

2

C interface is compliant with fast mode (400 kHz), 

and normal mode (100 kHz) I

2

C standards 

The transaction on the bus is started through a start condition (START) signal. START condition is defined as a HIGH to LOW 

transition on the data line while the SCL line is held HIGH. After START has been transmitted by the master, the bus is considered 
busy. The next byte of data transmitted after START contains the slave address in the first 7 bits, and the eighth bit tells whether 
the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system 
compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the 
master. The ninth clock pulse, following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The trans-
mitter must release the SDA line during the ACK period. The receiver must then pull the data line low so that it remains stable 
low during the high period of the acknowledge clock period.

Table 8. Serial Interface Pin Descriptions

SCL

I

2

C Serial Clock

SDA

I

2

C Serial Data

Window

T_TGT

T_WND

±

=