Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

Sensors
Freescale Semiconductor, Inc.

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The FIFO mode can be changed while in the Active mode. The Active mode must first be disabled (F_MODE = 00), before the 
mode can be switched between Fill mode, Circular mode, and Trigger mode.

A FIFO sample count exceeding the watermark event does not stop the FIFO from accepting new data. The FIFO update rate is 
dictated by the selected system ODR. 

•

In ACTIVE mode, the ODR is set by the DR bits (CTRL_REG1 register). 

•

When Auto-SLEEP is active, the ODR is set by the ASLP_RATE field (CTRL_REG1 register).

When a byte is read from the FIFO buffer, the oldest sample data in the FIFO buffer is returned (and also deleted from the front of 
the FIFO buffer), while the FIFO sample count is decremented by one. It is assumed that the host application will use the I

2

C multi-

byte read transaction to empty the FIFO.

The Trigger Configuration register configures which interrupt(s) may trigger the FIFO. 

7–6

F_MODE[1:0]

(1)(2)

1. Bit field can be written in ACTIVE mode.
2. Bit field can be written in STANDBY mode.

FIFO buffer overflow mode
00 FIFO is disabled. (default)
01 FIFO contains the most recent samples when overflowed (circular buffer). 

The oldest sample is discarded and replaced by a new sample.

10 FIFO stops accepting new samples when overflowed. 
11 Trigger mode. The FIFO will be in a circular mode up to the number of samples in the watermark. The 

FIFO will be in a circular mode until the trigger event occurs, after which the FIFO will continue to accept 
samples for 32-WMRK samples and then stop receiving further samples. This allows data to be collected 
both before and after the trigger event, and it is definable by the watermark setting.

• The FIFO is flushed whenever the FIFO is disabled, during an automatic ODR change (Auto-WAKE/

SLEEP), or transitioning from STANDBY mode to ACTIVE mode.

• Disabling the FIFO (F_MODE = 00) resets the F_OVF, F_WMRK_FLAG, F_CNT to zero.
• A FIFO overflow event (i.e., F_CNT = 32) will assert the F_OVF flag and a FIFO sample count equal to the 

sample count watermark (i.e., F_WMRK) asserts the F_WMRK_FLAG event flag.

5–0

F_WMRK[5:0]

(2)

FIFO Event Sample Count Watermark 
These bits set the number of FIFO samples required to trigger a watermark interrupt. 
A FIFO watermark event flag is raised when FIFO sample count F_CNT[5:0] 



 F_WMRK[5:0] watermark. 

• Setting the F_WMRK[5:0] to 00_0000 will disable the FIFO watermark event flag generation.
• Also used to set the number of pre-trigger samples in Trigger mode.
00_0000 (default)

—

—

Trig_TRANS

Trig_LNDPRT

Trig_PULSE

Trig_FF_MT

—

—

5

Trig_TRANS

0

• These trigger bits set are rising-edge sensitive, and are set by a 

low-to-high state change. 

• Trigger bits are reset by reading the appropriate source register.
1 This function can trigger the FIFO at its (the function’s) interrupt
0 This function has not asserted its interrupt.

4

Trig_LNDPRT

0

3

Trig_PULSE

0

2

Trig_FF_MT

0