Freescale Semiconductor Accelerometer Cube Demo MMA9559LKUBE MMA9559LKUBE 데이터 시트

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MMA9559LKUBE
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MMA955xL
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Freescale Semiconductor, Inc.
4.14
Slave SPI Timing
The following table
 describes the timing requirements for the SPI system. The “#” column refers to the numbered time period in 
Figure 10. SPI slave timing
Table 14. Slave SPI timing
#
Function
Symbol
Min
Max
Unit
Operating frequency
f
op
0
F
OPH
/4
Hz
1
SCLK period
t
SCLK
4
t
CYCH
2
Enable lead time
t
Lead
0.5
t
CYCH
3
Enable lag time
t
Lag
0.5
t
CYCH
4
Clock (SCLK) high or low time
t
WSCLK
200
ns
5
Data-setup time (inputs)
t
SU
15
ns
6
Data-hold time (inputs)
t
HI
25
ns
7
Access time
t
a
25
ns
8
SDO-disable time
t
dis
25
ns
9
Data valid (after SCLK edge)
t
v
25
ns
10
Data-hold time (outputs)
t
HO
0
ns
11
Rise time
Input
Output
t
RI
t
RO

25
25
ns
ns
12
Fall time
Input
Output
t
FI
t
FO

25
25
ns
ns
SCLK
(INPUT)
SDI
(INPUT)
SDO
(OUTPUT)
SS
(INPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT
SLAVE LSB OUT
BIT 6 . . . 1
NOTE:
 
SLAVE
SEE
NOTE
1. Not defined but normally MSB of character just received.
12
1
<
11
3
4
2
4
7
5
6
9
8
10
10