Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
FXOS8700CQ
Sensors
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
17
5
Digital Interfaces
5.1
I
2
C interface characteristics
Figure 5. I
2
C slave timing diagram
Table 9. I
2
C slave timing values
(1)
1. All values referred to VIH (min) and VIL (max) levels.
Parameter
Symbol
I
2
C Fast Mode
Unit
Min
Max
SCL Clock Frequency
f
SCL
0
400
kHz
Bus Free Time between STOP and START condition
t
BUF
1.3
μs
(Repeated) START Hold Time
t
HD;STA
0.6
μs
(Repeated) START Setup Time
t
SU;STA
0.6
μs
STOP Condition Setup Time
t
SU;STO
0.6
μs
SDA Data Hold Time
t
HD;DAT
0.05
0.9
(2)
2. This device does not stretch the LOW period (t
LOW
) of the SCL signal.
μs
SDA Valid Time
(3)
3. t
VD;DAT
= time for Data signal from SCL LOW to SDA output.
t
VD;DAT
0.9
μs
SDA Valid Acknowledge Time
(4)
4. t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
t
VD;ACK
0.9
μs
SDA Setup Time
t
SU;DAT
100
ns
SCL Clock Low Time
t
LOW
1.3
μs
SCL Clock High Time
t
HIGH
0.6
μs
SDA and SCL Rise Time
t
r
20 + 0.1 C
b
(5)
5. C
b
= total capacitance of one bus line in pF.
300
ns
SDA and SCL Fall Time
t
f
20 + 0.1 C
b
300
ns
Pulse width of spikes on SDA and SCL that must be suppressed by
internal input filter
internal input filter
t
SP
0
50
ns
handbook, full pagewidth
MSC610
S
Sr
tSU;STO
tSU;STA
tHD;STA
tHIGH
tLOW
tSU;DAT
tHD;DAT
tf
SDA
SCL
P
S
tBUF
tr
tf
tr
tSP
tHD;STA