Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
FXOS8700CQ
Sensors
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Freescale Semiconductor, Inc.
10.16.4 M_THS_COUNT (0x5A) register
This register sets the number of debounce sample counts required before a magnetic threshold event is triggered.The behavior
of the debounce counter is controlled by M_THS_X_MSB [m_ths_dbcntm].
of the debounce counter is controlled by M_THS_X_MSB [m_ths_dbcntm].
When the internal debounce counter reaches the M_THS_COUNT value a magnetic event flag is set. The debounce counter will
never increase beyond the M_THS_COUNT value. The time step used for the debounce sample count depends on the chosen
ODR. When hybrid mode is enabled, the effective ODR is reduced by a factor of two, which increases the debounce counter time
step by a factor of two from what is shown in
never increase beyond the M_THS_COUNT value. The time step used for the debounce sample count depends on the chosen
ODR. When hybrid mode is enabled, the effective ODR is reduced by a factor of two, which increases the debounce counter time
step by a factor of two from what is shown in
For example, an ODR of 100 Hz and a M_THS_COUNT value of 15 would result in a debounce response time of 150 ms. In
hybrid mode, the same settings would result in a debounce response time of 300 ms.
hybrid mode, the same settings would result in a debounce response time of 300 ms.
Table 192. M_THS_COUNT register
m_ths_cnt[7:0]
0b0000_0000
Table 193. M_THS_COUNT bit description
Field
Description
m_ths_cnt[7:0]
Magnetic threshold debounce count value.
Table 194. M_THS_COUNT relationship with the ODR
ODR (Hz)
Time step (ms)
M_CTRL_REG1[m_hms] = 0b01
M_CTRL_REG1[m_hms] = 0b11
800
N/A
N/A
400
2.5
5
200
5
10
100
10
20
50
20
40
12.5
80
160
6.25
160
320
1.56
641
1282