Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM 정보 가이드

 
 

Freescale Semiconductor

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The MSC8156 device targets high-bandwidth highly computational DSP applications and is optimized for 
3GPP, TD-SCDMA, 3G-LTE, and WiMAX applications. 

The MSC8156 devices are highly integrated DSP processors that contain six StarCore

®

 SC3850 DSP 

subsystems with 32 Kbyte L1 instruction cache per core, 32 Kbyte L1 data cache per core, 512 Kbyte L2 
unified instruction/data cache per core (can be configured as M2 Memory); 1056 Kbyte of shared M3, 
memory; two DDR memory controllers; a multi-accelerator platform engine (MAPLE-B) for Turbo 
decoding, Viterbi decoding, Fast Fourier Transform and Discrete Fourier Transform acceleration; two 
serial RapidIO interfaces; two Gigabit Ethernet controllers; a PCI-Express controller; four 256-channel 
time-division multiplexing (TDM) interfaces; a 16 bidirectional channels DMA controller; an SPI 
interface; a UART interface; and an I

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C interface. Each SC3850 DSP core has four ALUs each with a dual 

16 

× 16 MAC per ALU and performs at 8000 million multiply accumulates per second (MMACS) at 1 

GHz yielding a maximum total performance of 48000 MMACS per device. 

In each SC3850 core subsystem, the SC3850 core connects to the following:

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32 Kbyte 8-way level 1 instruction cache (L1 ICache)

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32 Kbyte 8-way level 1 data cache (L1 DCache)

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512 Kbyte 8-way level 2 unified instruction/data cache (L2 Cache/M2 Memory)

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Memory management unit (MMU)

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Enhanced programmable interrupt controller (EPIC)

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Debug and profiling unit (DPU)

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Two 32-bit timers