Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM 사용자 설명서

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HSSI Programming Model
MSC8156
 
 Reference Manual, Rev. 2
Freescale Semiconductor
  
15-67
15.8.32   SRDS Control Register 5 (SRDSnCR5)
Note:
Always write reserved bits with the value they return when read. That is, to program 
the register, read the value, modify the appropriate fields, and then write back the 
resulting value.
SRDSnCR5 contains functional control bits for the SerDes interface logic. 
Note:
SerDes Port 1 uses a base address of 0xFFFAC000. 
SerDes Port 2 uses a base address of 0xFFFAD000.
Table 15-36 describes the SRDSnCR5 fields.
Note:
Lane A corresponds to SerDes lane 0 and Lane B corresponds to SerDes lane 1
.
SRDSnCR5
SRDS Control Register 5
Offset 0x14
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SDFMA
SDFMB
Type
R/W
Reset
0
0
0
0
0
0
x
x
0
0
0
0
0
0
x
x
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDTXLA
SDTXLB
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note:
Reset values designated by x are determined by selected reset configuration.
Table 15-36.  SRDSnCR5 Field Descriptions
Bits
Reset
Description
31–26
0
Reserved. Write to zero for future compatibility.
SDFMA
25–24
xx
Lane A Digital Filter Bandwidth
Sets the bandwidth of the digital filter that 
optimizes for a given frequency offset.
Recommended setting per protocol:
• PCI Express: 01.
• SGMII: 00.
• Serial RapidIO: 00.
00
200 ppm (SGMII or Serial RapidIO 
protocol)
01
600 ppm (PCI Express)
10
Reserved.
11
Reserved.
23–18
0
Reserved. Write to zero for future compatibility.
SDFMB
17–16
0000xx
Lane B Digital Filter Bandwidth
Sets the bandwidth of the digital filter that 
optimizes for a given frequency offset.
Recommended setting per protocol:
• PCI Express: 01.
• SGMII: 00.
• Serial RapidIO: 00.
00
200 ppm (SGMII or Serial RapidIO 
protocol)
01
600 ppm (PCI Express)
10
Reserved.
11
Reserved.
15–11
0
Reserved. Write to zero for future compatibility.