Corsair 1024MB Server Memory Module PC2-5300 667MHz DDR2 CM72DD1024AR-667 사용자 설명서
제품 코드
CM72DD1024AR-667
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
73, 74, 192
RAS#, CAS#,
WE#
WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) defi ne the command
being entered.
being entered.
71, 190
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 defi ne to which device bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1 defi ne
which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during
the LOAD MODE command.
READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1 defi ne
which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during
the LOAD MODE command.
57, 58, 60, 61, 63, 70, 176,
177, 179, 180, 182, 183,
188
177, 179, 180, 182, 183,
188
A0-A12
(512MB), A0-
A13 (1GB)
(512MB), A0-
A13 (1GB)
Input
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for Read/Write commands,
to select one location out of the memory array in the respective bank.
A10 sampled during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the
opcode during a LOAD MODE command.
column address and auto precharge bit (A10) for Read/Write commands,
to select one location out of the memory array in the respective bank.
A10 sampled during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the
opcode during a LOAD MODE command.
Page 2
1024 MB DDR2 Server Memory Module
General Description
The CM72DD1024AR is a DDR2 Dual Inline Memory Module (DIMM), designed
for applications in which both per formance and density are critical.
This DIMM
includes Error Checking and Correcting (ECC) for maximum reliability, and has
registered address and control signals to enable fully con gured systems. These
modules are constructed using 1 GBit SDRAMs, and are fully compliant with
cations.
These DIMMs are constructed using 128MB x 8 SDRAMs in BGA packages.
The module also includes an EEPROM to support Serial Presence Detect (SPD)
requirements. Decoupling capacitors are mounted on the printed circuit board
for each SDRAM device, and On-Die Termination is prodived on all lines. The
synchronous design of these Corsair SDRAM DIMMs allows precise cycle control
with the use of the system clock. I/O transactions are possible on every clock
cycle. The high clock frequency and high density of this device enable a high
level of performance to be achieved in advanced workstations and servers.
Pin Defi nitions