Analog Devices AD9211 Evaluation Board AD9211-200EBZ AD9211-200EBZ 데이터 시트

 

Rev. 0 | Page 25 of 28 

Each row in the memory map table has eight address locations. 
The memory map is roughly divided into three sections: chip 
configuration register map (Address 0x00 to Address 0x02), 
transfer register map (Address 0xFF), and program register map 
(Address 0x08 to Address 0x2A).  

The Addr. (Hex) column of the memory map indicates the 
register address in hexadecimal, and the Default Value (Hex) 
column shows the default hexadecimal value that is already 
written into the register. The Bit 7 (MSB) column is the start of 
the default hexadecimal value given. For example, Hexadecimal 
Address 0x09, clock, has a hexadecimal default value of 0x01. 
This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,  
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The 
default value enables the duty cycle stabilizer. Overwriting this 
default so that Bit 0 = 0 disables the duty cycle stabilizer. For more 
information on this and other functions, consult the 

 

application note, Interfacing to High Speed ADCs via SPI. 

Undefined memory locations should not be written to other 
than their default values suggested in this data sheet. Addresses 
that have values marked as 0 should be considered reserved and 
have a 0 written into their registers during power-up.  

Coming out of reset, critical registers are preloaded with default 
values. These values are indicated in Table 13. Other registers 
do not have default values and retain the previous value when 
exiting reset.  

An explanation of various registers follows: “Bit is set” is 
synonymous with “bit is set to Logic 1” or “writing Logic 1 for 
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to 
Logic 0” or “writing Logic 0 for the bit.” 

00 chip_port_config 

0 

LSB 
first 

Soft 
reset 

1 1 Soft 

reset 

LSB first 

0 

0x18 

The nibbles 
should be 
mirrored by the 
user so that LSB 
or MSB first 
mode registers 
correctly, 
regardless of 
shift mode. 

01 

chip_id 

8-bit chip ID, Bits[7:0]  

AD9211 = 0x06 

Read-
only 

Default is unique 
chip ID, different 
for each device. 
This is a read-
only register.  

02 chip_grade 

0 

0 

0 

Speed 

grade: 

00 = 300 MSPS 
01 = 250 MSPS 
10 = 200 MSPS 

X X X  Read-

only 

Child ID used to 
differentiate 
graded devices. 

FF 

device_update 

0  0 0 0 0 0 0 SW 

transfer 

0x00 Synchronously 

transfers data 
from the master 
shift register to 
the slave.