Analog Devices AD9253 Evaluation Board AD9253-125EBZ AD9253-125EBZ 데이터 시트

 

Rev. 0 | Page 32 of 40 

The pins described in Table 15 comprise the physical interface 
between the user programming device and the serial port of the 

. The SCLK pin and the CSB pin function as inputs 

when using the SPI interface. The SDIO pin is bidirectional, 
functioning as an input during write phases and as an output 
during readback.  

The SPI interface is flexible enough to be controlled by either 
FPGAs or microcontrollers. One method for SPI configuration 
is described in detail in the 

controller-Based Serial Port Interface (SPI) Boot Circuit.  

The SPI port should not be active during periods when the full 
dynamic performance of the converter is required. Because the 
SCLK signal, the CSB signal, and the SDIO signal are typically 
asynchronous to the ADC clock, noise from these signals can 
degrade converter performance. If the on-board SPI bus is used for 
other devices, it may be necessary to provide buffers between 
this bus and the 

 to prevent these signals from transi-

tioning at the converter inputs during critical sampling periods. 

Some pins serve a dual function when the SPI interface is not 
being used. When the pins are strapped to DRVDD or ground 
during device power-on, they are associated with a specific 
function. Table 16 describes the strappable functions supported 
on the 

. 

In applications that do not interface to the SPI control registers, 
the SDIO/OLM pin, the SCLK/DTP pin, and the PDWN pin 
serve as standalone CMOS-compatible control pins. When the 
device is powered up, it is assumed that the user intends to use the 
pins as static control lines for the duty cycle stabilizer, output 
data format, and power-down feature control. In this mode, 
CSB should be connected to AVDD, which disables the serial 
port interface.  

When the device is in SPI mode, the PDWN pin (if enabled) 
remains active. For SPI control of power-down, the PDWN pin 
should be set to its default state. 

Table 16 provides a brief description of the general features that 
are accessible via the SPI. These features are described in detail 
in the 

via SPI. The 

 part-specific features are described in detail 

following Table 17, the external memory map register table. 

Power Mode 

Allows the user to set either power-down mode 
or standby mode 

Clock 

Allows the user to access the DCS, set the 
clock divider, set the clock divider phase, and 
enable the sync 

Offset 

Allows the user to digitally adjust the 
converter offset 

Test I/O 

Allows the user to set test modes to have 
known data on output bits 

Output Mode 

Allows the user to set the output mode  

Output Phase 

Allows the user to set the output clock polarity 

ADC Resolution 

Allows for power consumption scaling with 
respect to sample rate.