Atmel Evaluation Kit AT91SAM9260-EK AT91SAM9260-EK 데이터 시트

 6234C–ATARM–22-Mar-07

The silkscreen is wrong. The markings for BB and 1V8 are inverted.

The marking should be:

!

On J10 pin 1 (square pin): BB.

!

On J10 pin 3: 1V8.

The S2 footprint must never be shorted to select a JTAG mode, otherwise the chip can
be damaged. 

By default, the JTAGSEL input pin integrates a pull-down resistor (ICE mode). To select
the JTAG mode, connect the JTAGSEL input pin at VDDBU power.

In order to use the TWI in Fast Mode (up to 400 Kbits/s), the default 10 K

Ω

 resistors R44

and R45 should be replaced by smaller values (e.g., 2.2 K

Ω

). 

Note that there is no need to change the pull-up resistors if the TWI is used in Standard
Mode (up to 100 Kbits/s).

In the present schematics (block diagram p.10 and sheet 1/8, p.26), the MCLK and
BCLK sources implementation does not guarantee a correct phase relation as specified
in the AT73C213 datasheet.

Problem Fix/Workaround: 

In his own design, the user must make sure the BCLK and MCLK clocks generation
implements the timing specified in the AT73C213 datasheet.