Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트
제품 코드
AT91SAM9N12-EK
Signal Descriptions
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
A-7
A.4
Debug signals
Table A-3 describes the ARM926EJ-S processor debug signals.
Table A-3 Debug signals
Name
Direction
Description
COMMRX
Communications
channel receive
channel receive
Output
When HIGH, this signal denotes that the comms
channel receive buffer contains valid data waiting to
be read.
channel receive buffer contains valid data waiting to
be read.
COMMTX
Communications
channel transmit
channel transmit
Output
When HIGH, this signal denotes that the comms
channel transmit buffer is empty.
channel transmit buffer is empty.
DBGACK
Debug acknowledge
Output
When HIGH indicates that the processor is in debug
state.
state.
DBGDEWPT
Data watchpoint
Input
Asserted by external hardware to halt execution of
the processor for debug purposes. If HIGH at the end
of a data memory request cycle, it causes the
ARM926EJ-S processor to enter debug state.
the processor for debug purposes. If HIGH at the end
of a data memory request cycle, it causes the
ARM926EJ-S processor to enter debug state.
DBGEN
Debug enable
Input
Enables the debug features of the processor. This
signal must be tied LOW if debug is not required.
signal must be tied LOW if debug is not required.
DBGEXT[1:0]
EmbeddedICE-RT
external input
external input
Input
Inputs to the EmbeddedICE-RT logic that enable
breakpoints or watchpoints to be dependent on
external conditions.
breakpoints or watchpoints to be dependent on
external conditions.
DBGIEBKPT
Instruction breakpoint
Input
Asserted by external hardware to halt execution of
the processor for debug purposes. If HIGH at the end
of an instruction fetch, it causes the ARM926EJ-S
processor to enter debug state if that instruction
reaches the Execute stage of the processor pipeline.
the processor for debug purposes. If HIGH at the end
of an instruction fetch, it causes the ARM926EJ-S
processor to enter debug state if that instruction
reaches the Execute stage of the processor pipeline.
DBGINSTREXEC
Instruction executed
Output
Indicates that the instruction in the Execute stage of
the processor pipeline has been executed.
the processor pipeline has been executed.