Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트
제품 코드
AT91SAM9N12-EK
Programmer’s Model
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
2-11
The line length of the cache is determined by the Len field. The Len field is bits [13:12]
for the DCache and bits [1:0] for the ICache. Table 2-9 shows the line length encoding.
for the DCache and bits [1:0] for the ICache. Table 2-9 shows the line length encoding.
The cache type register values for an ARM926EJ-S processor with the following
configuration are shown in Table 2-10:
configuration are shown in Table 2-10:
•
separate instruction and data caches
•
DCache size = 8KB, ICache size = 16KB
•
associativity = 4-way
•
line length = eight words
•
caches use write-back, register 7 for cache cleaning, and Format C for cache
lockdown.
lockdown.
See Cache Lockdown Register c9 on page 2-26 for more details on Format C for cache
lockdown.
lockdown.
Table 2-9 Line length encoding
Len field
Cache line length
b10
8 words (32 bytes)
Other values
Reserved
Table 2-10 Example Cache Type Register format
Function
Register bits
Value
Reserved
[31:29]
b000
Ctype
[28:25]
b1110
S
[24]
b1 = Harvard cache
Dsize
Reserved
[23:22]
b00
Size
[21:18]
b0100 = 8KB
Assoc
[17:15]
b010 = 4-way
M
[14]
b0
Len
[13:12]
b10 = 8 words per line (32 bytes)