Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK 데이터 시트
제품 코드
AT91SAM9G25-EK
1030
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
45.6.26 EMAC Statistic Registers
These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read fre-
quently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in
the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register
block contains the following registers.
quently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in
the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register
block contains the following registers.
45.6.26.1 Pause Frames Received Register
Name:
EMAC_PFR
Address:
0xF802C03C
Access:
Read-write
• FROK: Pause Frames received OK
A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit 8 set in
network configuration register) and has no FCS, alignment or receive symbol errors.
network configuration register) and has no FCS, alignment or receive symbol errors.
45.6.26.2 Frames Transmitted OK Register
Name:
EMAC_FTO
Address:
0xF802C040
Access:
Read-write
• FTOK: Frames Transmitted OK
A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
FROK
7
6
5
4
3
2
1
0
FROK
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
FTOK
15
14
13
12
11
10
9
8
FTOK
7
6
5
4
3
2
1
0
FTOK