Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK 데이터 시트
제품 코드
AT91SAM9G25-EK
411
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
30.3
DDRSDRC Module Diagram
Figure 30-1. DDRSDRC Module Diagram
DDRSDRC is partitioned in two blocks (see
):
z
An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four AHB masters and
integrates an arbiter.
integrates an arbiter.
z
A controller that translates AHB requests (Read/Write) in the SDRAM protocol.
Memory Controller
Finite
S
t
a
te M
a
chine
S
DRAM
S
ign
a
l M
a
n
a
gement
Addr, DQM
D
a
t
a
A
s
ynchrono
us
Timing
Refre
s
h M
a
n
a
gement
DDR-
S
DR
Device
s
Power M
a
n
a
gement
DQ
S
r
as
,c
as
,we
cke
clk/nclk
odt
DDR-
S
DR Controller
Interconnect M
a
trix
Inp
u
t
S
t
a
ge
Inp
u
t
S
t
a
ge
Inp
u
t
S
t
a
ge
O
u
tp
u
t
S
t
a
ge
Ar
b
iter
APB
AHB
S
l
a
ve Interf
a
ce 0
AHB
S
l
a
ve Interf
a
ce 1
AHB
S
l
a
ve Interf
a
ce 2
AHB
S
l
a
ve Interf
a
ce
3
Inp
u
t
S
t
a
ge
Interf
a
ce APB