Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK 데이터 시트

991

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address
checker, statistics and control registers, receive and transmit blocks, and a DMA interface.

The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast
and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external
address match signal.

The statistics register block contains registers for counting various types of event associated with transmit and receive
operations. These registers, along with the status words stored in the receive buffer list, enable software to generate
network management statistics compatible with IEEE 802.3.

z

Supports MII Interface to the physical layer

z

Compatible with IEEE Standard 802.3

z

10 and 100 Mbit/s Operation

z

Full- and Half-duplex Operation

z

Statistics Counter Registers

z

Interrupt Generation to Signal Receive and Transmit Completion

z

DMA Master on Receive and Transmit Channels

z

Transmit and Receive FIFOs

z

Automatic Pad and CRC Generation on Transmitted Frames

z

Automatic Discard of Frames Received with Errors

z

Address Checking Logic Supports Up to Four Specific 48-bit Addresses

z

Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory

z

Hash Matching of Unicast and Multicast Destination Addresses

z

Physical Layer Management through MDIO Interface

z

Half-duplex Flow Control by Forcing Collisions on Incoming Frames

z

Full-duplex Flow Control with Recognition of Incoming Pause Frames 

z

Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and 

Priority Tagged Frames

z

Multiple Buffers per Receive and Transmit Frame

z

Jumbo Frames Up to 10240 bytes Supported