Atmel SAM4S Xplained Pro Starter and Evaluation Kit ATSAM4S-XPRO ATSAM4S-XPRO 데이터 시트
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제품 코드
ATSAM4S-XPRO
381
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
22.
Cortex-M Cache Controller (CMCC)
22.1
Description
The Cortex-M Cache Controller (CMCC) is a four-way set associative unified cache controller. It integrates a
controller, a tag directory, data memory, metadata memory and a configuration interface.
22.2
Embedded Characteristics
Physically addressed and physically tagged
L1 data cache set to 2 Kbytes
L1 cache line size set to 16 Bytes
L1 cache integrates 32-bit bus master interface
Unified Direct mapped cache architecture
Unified four-way set associative cache architecture
Write through cache operations, read allocate
Round Robin victim selection policy
Event Monitoring, with one programmable 32-bit counter
Configuration registers accessible through Cortex-M Private Peripheral Bus
Cache Interface includes cache maintenance operations registers