Atmel SAM4S Xplained Pro Starter and Evaluation Kit ATSAM4S-XPRO ATSAM4S-XPRO 데이터 시트
제품 코드
ATSAM4S-XPRO
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
70
12.4.2.1 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region has a defined
memory type, and some regions have additional memory attributes. The memory type and attributes determine the
behavior of accesses to the region.
Memory Types
Normal
The processor can re-order transactions for efficiency, or perform speculative reads.
The processor can re-order transactions for efficiency, or perform speculative reads.
Device
The processor preserves transaction order relative to other transactions to Device or Strongly-ordered
The processor preserves transaction order relative to other transactions to Device or Strongly-ordered
memory.
Strongly-ordered
The processor preserves transaction order relative to all other transactions.
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can
buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory.
Additional Memory Attributes
Shareable
For a shareable memory region, the memory system provides data synchronization between bus masters in
For a shareable memory region, the memory system provides data synchronization between bus masters in
a system with multiple bus masters, for example, a processor with a DMA controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, the software must ensure data
coherency between the bus masters.
Execute Never (XN)
Means the processor prevents instruction accesses. A fault exception is generated only on execution of an
Means the processor prevents instruction accesses. A fault exception is generated only on execution of an
instruction executed from an XN region.
12.4.2.2 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not
guarantee that the order in which the accesses complete matches the program order of the instructions, providing
this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on
two memory accesses completing in program order, the software must insert a memory barrier instruction between
the memory access instructions, see
However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered
memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of
the memory accesses is described below.
Where:
–
Means that the memory system does not guarantee the ordering of the accesses.
Table 12-3.
Ordering of the Memory Accesses Caused by Two Instructions
A2
Normal
Access
Device Access
Strongly-
ordered
Access
A1
Non-
shareable
Shareable
Normal
A
ccess
–
–
–
–
Device access, non-shareable
–
<
–
<
Device access, shareable
–
–
<
<
Strongly-ordered access
–
<
<
<