Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트
제품 코드
AT91SAM9N12-EK
527
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 33-9. Data OUT Transfer for Non Ping-pong Endpoints
An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and
microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would
accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO.
microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would
accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO.
Using Endpoints With Ping-pong Attributes
During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a
constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data
payload is received by the USB device. Thus two banks of memory are used. While one is available for the
microcontroller, the other one is locked by the USB device.
constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data
payload is received by the USB device. Thus two banks of memory are used. While one is available for the
microcontroller, the other one is locked by the USB device.
Figure 33-10. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints
When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions:
1.
The host generates a Data OUT packet.
2.
This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0.
ACK
PID
Data OUT
NAK
PID
PID
PID
PID
PID
Data OUT2
ACK
Data OUT
Data OUT 1
USB Bus
Packets
Packets
RX_DATA_BK0
Set by USB Device
Cleared by Firmware,
Data Payload Written in FIFO
Data Payload Written in FIFO
FIFO (DPR)
Content
Content
Written by USB Device
Microcontroller Read
Data OUT 1
Data OUT 1
Data OUT 2
Host Resends the Next Data Payload
Microcontroller Transfers Data
Host Sends Data Payload
Data OUT2
Data OUT2
Host Sends the Next Data Payload
Written by USB Device
(UDP_CSRx)
Interrupt Pending
USB Device
USB Bus
Read
Write
Write and Read at the Same Time
1st Data Payload
2nd Data Payload
3rd Data Payload
3rd Data Payload
2nd Data Payload
1st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
Microcontroller
Endpoint 1
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 1