Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 데이터 시트
제품 코드
AT91SAM9N12-EK
60
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 11-6. External Interrupt Edge Triggered Source
Figure 11-7. External Interrupt Level Sensitive Source
Figure 11-8. Internal Interrupt Edge Triggered Source
Figure 11-9. Internal Interrupt Level Sensitive Source
Maximum FIQ Latency = 4 Cycles
Maximum IRQ Latency = 4 Cycles
nFIQ
nIRQ
MCK
IRQ or FIQ
(Positive Edge)
IRQ or FIQ
(Negative Edge)
Maximum IRQ
Latency = 3 Cycles
Maximum FIQ
Latency = 3 cycles
MCK
IRQ or FIQ
(High Level)
IRQ or FIQ
(Low Level)
nIRQ
nFIQ
MCK
nIRQ
Peripheral Interrupt
Becomes Active
Maximum IRQ Latency = 4.5 Cycles
MCK
nIRQ
Maximum IRQ Latency = 3.5 Cycles
Peripheral Interrupt
Becomes Active