Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK 데이터 시트

1034

SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

The same signals are used internally for both the RMII and the MII operations. The RMII maps the signals in a more pin-
efficient manner. The transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is 
clocked at twice the rate. The carrier sense and data valid signals are combined into the ECRSDV signal. This signal 
contains information on carrier sense, FIFO status, and validity of the data. Transmit error bit (ETXER) and collision 
detect (ECOL) are not used in RMII mode.

Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and 
receive circuits are disabled. See the description of the network control register and network configuration register earlier 
in this document.

To change loop-back mode, the following sequence of operations must be followed:

1.

Write to network control register to disable transmit and receive circuits.

2.

Write to network control register to change loop-back mode.

3.

Write to network control register to re-enable transmit or receive circuits.

Note:

These writes to network control register cannot be combined in any way.

Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data 
structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor entries 
as defined in 

To create the list of buffers:

1.

Allocate a number (n) of buffers of 128 bytes in system memory.

2.

Allocate an area 2n words for the receive buffer descriptor entry in system memory and create n entries in this list. 
Mark all entries in this list as owned by EMAC, i.e., bit 0 of word 0 set to 0.

3.

If less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set to 1).

4.

Write address of receive buffer descriptor entry to EMAC register receive_buffer queue pointer.

Receive Buffer Queue Pointer

(MAC Register)

Receive Buffer 0

Receive Buffer 1

Receive Buffer N

Receive Buffer Descriptor List

(In memory)

(In memory)