Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD 데이터 시트
제품 코드
ATSAM4S-XPLD
107
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with
the additional restrictions:
the additional restrictions:
The user must not specify the S suffix
The second operand must be a constant in the range 0 to 4095.
Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00 before
performing the calculation, making the base address for the calculation word-aligned.
performing the calculation, making the base address for the calculation word-aligned.
Note: To generate the address of an instruction, the constant based on the value of the PC must be
adjusted. ARM recommends to use the ADR instruction instead of ADD or SUB with Rn equal to the PC,
because the assembler automatically calculates the correct constant for the ADR instruction.
adjusted. ARM recommends to use the ADR instruction instead of ADD or SUB with Rn equal to the PC,
because the assembler automatically calculates the correct constant for the ADR instruction.
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Condition Flags
If
S
is specified, these instructions update the N, Z, C and V flags according to the result.
Examples
ADD R2, R1, R3 ; Sets the flags on the result
SUBS R8, R6, #240 ; Subtracts contents of R4 from 1280
RSB R4, R4, #1280 ; Only executed if C flag set and Z
ADCHI R11, R0, R3 ; flag clear.
Multiword Arithmetic Examples
The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer
contained in R0 and R1, and place the result in R4 and R5.
contained in R0 and R1, and place the result in R4 and R5.
64-bit Addition Example
ADDS R4, R0, R2 ; add the least significant words
ADC R5, R1, R3 ; add the most significant words with carry
Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a 96-bit
integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9,
and R2.
integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9,
and R2.
96-bit Subtraction Example
SUBS R6, R6, R9 ; subtract the least significant words
SBCS R9, R2, R1 ; subtract the middle words with carry
SBC R2, R8, R11 ; subtract the most significant words with carry