Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD 데이터 시트

 524

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Notes: 1. Reset value depends on the product implementation.

2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.

3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the 

PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was 
disabled.

4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have 

occurred.

Note:

If an offset is not listed in the table it must be considered as reserved.

0x0120
to
0x014C

Reserved

0x150

Parallel Capture Mode Register

PIO_PCMR

Read-write

0x00000000

0x154

Parallel Capture Interrupt Enable Register

PIO_PCIER

Write-only

–

0x158

Parallel Capture Interrupt Disable Register

PIO_PCIDR

Write-only

–

0x15C

Parallel Capture Interrupt Mask Register

PIO_PCIMR

Read-only

0x00000000

0x160

Parallel Capture Interrupt Status Register

PIO_PCISR

Read-only

0x00000000

0x164

Parallel Capture Reception Holding Register

PIO_PCRHR

Read-only

0x00000000

0x0168
to
0x018C

Reserved for PDC Registers