Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD 데이터 시트
제품 코드
ATSAM4S-XPLD
662
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.5 TWI Clock Waveform Generator Register
Name: TWI_CWGR
Address:
0x40018010 (0), 0x4001C010 (1)
Access: Read-write
Reset:
0x00000000
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
CKDIV
15
14
13
12
11
10
9
8
CHDIV
7
6
5
4
3
2
1
0
CLDIV
T
low
CLDIV
(
2
CKDIV
×
(
)
4
)
+
T
MCK
×
=
T
high
CHDIV
(
2
CKDIV
×
(
)
4
)
+
T
MCK
×
=