Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO 데이터 시트

381

Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register 
will also be reflected in the Interrupt Enable Set register (INTENSET).

INTENCLR

0x0C

0x00

Write-Protected

z

Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.

z

Bit 2 – RXC: Receive Complete Interrupt Enable
0: Receive Complete interrupt is disabled.

1: Receive Complete interrupt is enabled.

Writing a zero to this bit has no effect. 

Writing a one to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete 
interrupt.

z

Bit 1 – TXC: Transmit Complete Interrupt Enable
0: Transmit Complete interrupt is disabled.

1: Transmit Complete interrupt is enabled.

Writing a zero to this bit has no effect. 

Writing a one to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete 
interrupt.

z

Bit 0 – DRE: Data Register Empty Interrupt Enable
0: Data Register Empty interrupt is disabled.

1: Data Register Empty interrupt is enabled.

Writing a zero to this bit has no effect. 

Writing a one to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register 
Empty interrupt.

Bit

7

6

5

4

3

2

1

0

Access

R

R

R

R

R

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0