Linear Technology LTC4226CUD-2 Demoboard : Dual Hot Swap Controller with Auto-Retry DC1627A-B DC1627A-B 데이터 시트

제품 코드

DC1627A-B

LTC4226

4226f

pin FuncTions

CLS: Three-State Current Limit Select Input. Tying this pin

low enables 1.5

× current limit; opening this pin enables 2×

current limit and tying this pin high (above 2V) enables 3

current limit. A higher current limit selection permits larger

current transients to pass without invoking current limiting.

The CLS pin permits dynamic current limit selection. The

three input states configure the preset current limit volt-

age V

LIMIT

to approximately 1.5

×, 2× or 3× of 1.15 • V

Exposed Pad: The exposed pad may be left open or con-

nected to device ground.
FAULT1, FAULT2: FAULT Input/Output Status. When the

FTMR pin has reached the V

FTMR(H)

threshold, the fault

status is set active and the FAULT pin output pulls low.

When fault is inactive, a 10µA current source pulls this

pin up to a diode below its internal supply voltage. Pulling

the FAULT pin low turns off the external MOSFET without

affecting the FTMR pin status. The FAULT pin is not latched.
FTMR1, FTMR2: Fault Timer. A capacitor sets the dual-

rate fault timer durations: circuit breaker CB timeout and

current limit CL timeout. The FTMR pin pulls up with

FTMR(CB)

when the sense resistor voltage is between V

and V

LIMIT

. The FTMR pin pulls up with I

FTMR(CL)

when

the sense resistor voltage is at or above V

LIMIT

. FTMR

pulls low with I

FTMR(DEF)

when the sense resistor volt-

age falls below V

. When the FTMR voltage reaches the

FTMR(H)

threshold, the fault status is activated. To reset

FTMR, the ON pin can be pulled low or the correspond-

ing supply voltage can be pulled below the undervoltage

lockout threshold. The capacitor on the FTMR pin is pulled

to GND with I

FTMR(RST)

to clear the fault status. For the

LTC4226-1 latchoff option, the MOSFET remains off until

faults are cleared by cycling the ON pin or by an under-

voltage condition on the corresponding supply. For the

LTC4226-2 auto-retry option, after a t

D(COOL)

delay, FTMR

is reset, the fault status is cleared, and the GATE begins

to ramp up. The LTC4226-2 can be forced to restart by

cycling the ON pin or by an undervoltage condition on the

corresponding supply.

GATE1, GATE2: Gate Drive for External MOSFET. The gate

driver controls the external N-channel MOSFET switch

by applying a voltage across the GATE and OUT pins

which connect to the MOSFET gate and source pins. A

charge pump sources 9µA at the GATE pin to turn on the

external MOSFET. When the MOSFET is on, the GATE pin

voltage is clamped at ∆V

GATE

above the OUT pin. During

turn-off, the GATE pin is discharged by a 3mA pull-down

with about 2.85mA of current flowing to the OUT pin. In

a severe fault, the GATE pin is discharged to the OUT pin

with a minimum of 100mA. When the MOSFET is off,

the GATE pin is pulled towards ground with 150µA and

a voltage clamps limits the GATE voltage to a diode drop

below the OUT pin.
GND: Device ground
ON1, ON2: ON Control Inputs. The ON pins have a 1.23V

threshold with 50mV of hysteresis. A high input turns on

the external MOSFET with a 10ms delay. A low input turns

off the external MOSFET and resets circuit breaker faults.
OUT1, OUT2: Gate Drive Return. Connect this pin to the

source of the external N-channel MOSFET switch. This pin

provides a return for the gate pull-down circuit. When the

GATE pin is below the OUT pin, the internal clamp diode

draws current from this OUT pin.
SENSE1, SENSE2: Current Sense Negative Input. The

circuit breaker comparator and the current limit amplifier

monitor the voltage across the sense resistor. The current

limiting amplifier controls the GATE of the external MOSFET

to keep the sense resistor voltage at V

LIMIT

. The current

limit is set higher than the circuit breaker to accommodate

noisy loads that momentarily exceed the circuit breaker

comparator threshold.
V

CC1

, V

CC2

: Supply Voltage and Current Sense Positive

Input. An undervoltage lockout circuit disables the MOS-

FET switch until V

is above the lockout voltage V

CC(UVL)

for 50ms.