Linear Technology DC1266A-A - LTC2453 16-bit I²C Differential ADC in 3x2 DFN, req DC590 DC1266A-A DC1266A-A 데이터 시트
제품 코드
DC1266A-A
LTC2453
7
2453fc
CONVERTER OPERATION
Converter Operation Cycle
The LTC2453 is a low-power, fully differential, delta-sigma
The LTC2453 is a low-power, fully differential, delta-sigma
analog-to-digital converter with an I
2
C interface. Its oper-
ation, as shown in Figure 1, is composed of three suc-
cessive states: CONVERSION, SLEEP and DATA OUTPUT.
Initially, at power up, the LTC2453 performs a conversion.
Initially, at power up, the LTC2453 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, power consumption is
reduced by several orders of magnitude. The part remains
in the sleep state as long as it is not addressed for a read
operation. The conversion result is held indefinitely in a
static shift register while the part is in the sleep state.
APPLICATIONS INFORMATION
edges of SCL, allowing the user to reliably latch data on
the rising edge of SCL. A new conversion is initiated by
a stop condition following a valid read operation, or by
the conclusion of a complete read cycle (all 16 bits read
out of the device).
Power-Up Sequence
When the power supply voltage (V
Power-Up Sequence
When the power supply voltage (V
CC
) applied to the con-
verter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When V
When V
CC
rises above this threshold, the converter gener-
ates an internal power-on reset (POR) signal for approxi-
mately 0.5ms. The POR signal clears all internal registers.
Following the POR signal, the LTC2453 starts a conversion
cycle and follows the succession of states described in
Figure 1. The first conversion result following POR is ac-
curate within the specifications of the device if the power
supply voltage V
CC
is restored within the operating range
(2.7V to 5.5V) before the end of the POR time interval.
Ease of Use
The LTC2453 data output has no latency, filter settling
The LTC2453 data output has no latency, filter settling
delay or redundant results associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog input voltages requires no special actions.
The LTC2453 performs offset calibrations every conver-
The LTC2453 performs offset calibrations every conver-
sion. This calibration is transparent to the user and has
no effect upon the cyclic operation described previ-
ously. The advantage of continuous calibration is extreme
stability of the ADC performance with respect to time and
temperature.
The LTC2453 includes a proprietary input sampling scheme
The LTC2453 includes a proprietary input sampling scheme
that reduces the average input current by several orders
of magnitude when compared to traditional delta-sigma
architectures. This allows external filter networks to in-
terface directly to the LTC2453. Since the average input
sampling current is 50nA, an external RC lowpass filter
using a 1k
Ω and 0.1µF results in <1LSB additional error.
Additionally, there is negligible leakage current between
IN
+
and IN
–
.
READ
ACKNOWLEDGE
DATA OUTPUT
YES
YES
2453 F01
STOP
OR READ
16-BITS
SLEEP
CONVERSION
POWER-ON RESET
NO
NO
Figure 1. LTC2453 State Diagram
The device will not acknowledge an external request during
the conversion state. After a conversion is finished, the
device is ready to accept a read request. The LTC2453’s
address is hard-wired at 0010100. Once the LTC2453 is
addressed for a read operation, the device begins output-
ting the conversion result under the control of the serial
clock (SCL). There is no latency in the conversion result.
The data output is 16 bits long and contains a 15-bit plus
sign conversion result. Data is updated on the falling