Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD 데이터 시트

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

where:
opis one of:
QADD Saturating 32-bit add.
QADD8 Saturating four 8-bit integer additions.
QADD16 Saturating two 16-bit integer additions.
QSUB Saturating 32-bit subtraction.
QSUB8 Saturating four 8-bit integer subtraction.
QSUB16 Saturating two 16-bit integer subtraction.
condis an optional condition code, see 

.

Rdis the destination register.
Rn, Rmare registers holding the first and second operands.
Operation
These instructions add or subtract two, four or eight values from the first and second operands and then writes a 

signed saturated value in the destination register. 
The QADD and QSUB instructions apply the specified add or subtract, and then saturate the result to the signed 

range -2

–1

≤ x ≤ 2

–1

-1, where x is given by the number of bits applied in the instruction, 32, 16 or 8.

If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the 

QADD and QSUB instructions set the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. The 8-bit 

and 16-bit QADD and QSUB instructions always leave the Q flag unchanged.
To clear the Q flag to 0, the MSR instruction must be used; see 

.

To read the state of the Q flag, the MRS instruction must be used; see 

Restrictions
Do not use SP and do not use PC

Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.