Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트
제품 코드
AT32UC3A3-XPLD
180
32072H–AVR32–10/2012
AT32UC3A3
15.5.1
I/O Lines
The SMC signals pass through the External Bus Interface (EBI) module where they are multi-
plexed. The user must first configure the I/O Controller to assign the EBI pins corresponding to
SMC signals to their peripheral function. If the I/O lines of the EBI corresponding to SMC signals
are not used by the application, they can be used for other purposes by the I/O Controller.
plexed. The user must first configure the I/O Controller to assign the EBI pins corresponding to
SMC signals to their peripheral function. If the I/O lines of the EBI corresponding to SMC signals
are not used by the application, they can be used for other purposes by the I/O Controller.
15.5.2
Clocks
The clock for the SMC bus interface (CLK_SMC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
SMC before disabling the clock, to avoid freezing the SMC in an undefined state.
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
SMC before disabling the clock, to avoid freezing the SMC in an undefined state.
15.6
Functional Description
15.6.1
Application Example
Figure 15-2. SMC Connections to Static Memory Devices
15.6.2
External Memory Mapping
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address
up to 16Mbytes of memory.
up to 16Mbytes of memory.
If the physical memory device connected on one chip select is smaller than 16Mbytes, it wraps
around and appears to be repeated within this space. The SMC correctly handles any valid
access to the memory device within the page (see
around and appears to be repeated within this space. The SMC correctly handles any valid
access to the memory device within the page (see
A[23:0] is only significant for 8-bit memory, A[23:1] is used for 16-bit memory23.
128K x 8
SRAM
D0-D7
CS
OE
WE
A0-A16
128K x 8
SRAM
D0-D7
CS
OE
WE
A0-A16
D0-D15
NWR1/NBS1
A0/NBS0
NWR0/NWE
NCS0
NCS2
NCS1
NCS3
NCS5
NCS4
NRD
NRD
A2-A18
Static Memory
Controller
NWR0/NWE
NWR1/NBS1
D8-D15
D0-D7
A2-A18
A2-A18