Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트

32072H–AVR32–10/2012

Figure 15-11. Write Cycle

The write cycle time is defined as the total duration of the write cycle, that is, from the time where
address is set on the address bus to the point where address may change. The total write cycle
time is equal to:

Similarly,

All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of CLK_SMC cycles. To ensure that the NWE and NCS timings are coherent, the user must
define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time
and NCS (write) hold times as:

And,

CLK_SMC

A[AD_MSB:2]

NBS0, NBS1, 

A0, A1

NWE

NCS

NWESETUP

NWEPULSE

NCSWRPULSE

NCSWRSETUP

NWECYCLE

NWEHOLD

NCSWRHOLD

+

+

=

+

+

=

–

–

=

–

–

=