Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트

32072H–AVR32–10/2012

The user must also make sure that the system stack is large enough so that any event is able to
push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.

When an event other than scall or debug request is received by the core, the following actions
are performed atomically:

1.

The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and 
GM bits in the Status Register are used to mask different events. Not all events can be 
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and 
Bus Error) can not be masked. When an event is accepted, hardware automatically 
sets the mask bits corresponding to all sources with equal or lower priority. This inhibits 
acceptance of other events of the same or lower priority, except for the critical events 
listed above. Software may choose to clear some or all of these bits after saving the 
necessary state if other priority schemes are desired. It is the event source’s respons-
ability to ensure that their events are left pending until accepted by the CPU.

2.

When a request is accepted, the Status Register and Program Counter of the current 
context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, reg-
isters R8-R12 and LR are also automatically stored to stack. Storing the Status 
Register ensures that the core is returned to the

 

previous execution mode when the 

current event handling is completed. When exceptions occur, both the EM and GM bits 
are set, and the application may manually enable nested exceptions if desired by clear-
ing the appropriate bit. Each exception handler has a dedicated handler address, and 
this address uniquely identifies the exception source.

3.

The Mode bits are set to reflect the priority of the accepted event, and the correct regis-
ter file bank is selected. The address of the event handler, as shown in Table 4-4, is 
loaded into the Program Counter.

The execution of the event handler routine then continues from the effective address calculated.

The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Address Register are popped from the system stack and restored to the Status Reg-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains information allowing the core to resume operation in the previous execution mode. This
concludes the event handling.

The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is
designed so that  privileged routines can be called from any context. This facilitates sharing of
code between different execution modes. The scall mechanism is designed so that a minimal
execution cycle overhead is experienced when performing supervisor routine calls from time-
critical event handlers.

The scall instruction behaves differently depending on which mode it is called from. The behav-
iour is detailed in the instruction set reference. In order to allow the scall routine to return to the
correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC
CPU, scall and rets uses the system stack to store the return address and the status register.

The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by
the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the