Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트

32072H–AVR32–10/2012

Figure 19-1. DMA Controller (DMACA) Block Diagram

In order to use this module, other parts of the system must be configured correctly, as described
below.

The pins used for interfacing the compliant external devices may be multiplexed with GPIO lines.
The user must first program the GPIO controller to assign the DMACA pins to their peripheral
functions. 

To prevent bus errors the DMACA operation must be terminated before entering sleep mode.

The CLK_DMACA to the DMACA is generated by the Power Manager (PM). Before using the
DMACA, the user must ensure that the DMACA clock is enabled in the power manager.

The DMACA interface has an interrupt line connected to the Interrupt Controller. Handling the
DMACA interrupt requires programming the interrupt controller before configuring the DMACA.

Both the source peripheral and the destination peripheral must be set up correctly prior to the
DMA transfer.

HSB Slave 

I/F

HSB Master 

I/F

CFG

Interrupt 

Generator

FIFO

Channel 0

SRC 
FSM

DST 

FSM

Channel 1

DMA Controller

irq_dma

HSB Slave

HSB Master