Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트

32072H–AVR32–10/2012

– ii. Set up the transfer characteristics, such as:

– Transfer width for the source in the SRC_TR_WIDTH field.

– Transfer width for the destination in the DST_TR_WIDTH field.

– Source master layer in the SMS field where source resides.

– Destination master layer in the DMS field where destination resides.

– Incrementing/decrementing or fixed address for source in SINC field.

– Incrementing/decrementing or fixed address for destination in DINC field.

e.

Write the channel configuration information into the CFGx register for channel x.

– i. Designate the handshaking interface type (hardware or software) for the source 

and destination peripherals. This is not required for memory. This step requires 
programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ 
activates the hardware handshaking interface to handle source/destination requests. 
Writing a ‘1’ activates the software handshaking interface to handle 
source/destination requests.

– ii. If the hardware handshaking interface is activated for the source or destination 

peripheral, assign a handshaking interface to the source and destination peripheral. 
This requires programming the SRC_PER and DEST_PER bits, respectively.

4.

After the DMACA selected channel has been programmed, enable the channel by writ-
ing a ‘1’ to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is 
enabled.

5.

Source and destination request single and burst DMA transactions to transfer the block 
of data (assuming non-memory peripherals). The DMACA acknowledges at the com-
pletion of every transaction (burst and single) in the block and carry out the block 
transfer.

6.

Once the transfer completes, hardware sets the interrupts and disables the channel. At 
this time you can either respond to the Block Complete or Transfer Complete interrupts, 
or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to 
detect when the transfer is complete.

1.

Read the Channel Enable register to choose a free (disabled) channel.

2.

Set up the chain of Linked List Items (otherwise known as block descriptors) in memory. 
Write the control information in the LLI.CTLx register location of the block descriptor for 
each LLI in memory (see 

) for channel x. For example, in the 

register, you can program the following:

a.

Set up the transfer type (memory or non-memory peripheral for source and desti-
nation) and flow control device by programming the TT_FC of the CTLx register.

b.

Set up the transfer characteristics, such as:

– i. Transfer width for the source in the SRC_TR_WIDTH field.

– ii. Transfer width for the destination in the DST_TR_WIDTH field.

– iii. Source master layer in the SMS field where source resides.

– iv. Destination master layer in the DMS field where destination resides.

– v. Incrementing/decrementing or fixed address for source in SINC field.

– vi. Incrementing/decrementing or fixed address for destination DINC field.

3.

Write the channel configuration information into the CFGx register for channel x.