Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트

32072H–AVR32–10/2012

Figure 19-12. DMA Transfer Flow for Source and Destination Address Auto-reloaded

1.

Read the Channel Enable register to choose a free (disabled) channel.

2.

Set up the chain of linked list items (otherwise known as block descriptors) in memory. 
Write the control information in the LLI.CTLx register location of the block descriptor for 
each LLI in memory for channel x. For example, in the register you can program the 
following:

a.

Set up the transfer type (memory or non-memory peripheral for source and desti-
nation) and flow control peripheral by programming the TT_FC of the CTLx register.

b.

Set up the transfer characteristics, such as:

– i. Transfer width for the source in the SRC_TR_WIDTH field.

– ii. Transfer width for the destination in the DST_TR_WIDTH field.

– iii. Source master layer in the SMS field where source resides.

– iv. Destination master layer in the DMS field where destination resides.

– v. Incrementing/decrementing or fixed address for source in SINC field.

– vi. Incrementing/decrementing or fixed address for destination DINC field.

Channel Enabled by

software

Block Transfer

Reload SARx, DARx, CTLx

Channel Disabled by
hardware

Block Complete interrupt

generated here

DMAC transfer Complete 

interrupt generated here

yes

no

yes

Stall until block complete

interrupt cleared by software 

CTLx.INT_EN=1

&&

MASKBLOCK[x]=1?

no

Is DMAC in Row1 of 

DMAC State Machine Table?