Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트
제품 코드
AT32UC3A3-XPLD
448
32072H–AVR32–10/2012
AT32UC3A3
Figure 22-4. Transfer Format
22.8.2
Operation
The TWIS has two modes of operation:
• Slave transmitter mode
• Slave receiver mode
A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is
assigned an address and responds to requests from the master. These modes are described in
the following chapters.
assigned an address and responds to requests from the master. These modes are described in
the following chapters.
Figure 22-5. Typical Application Block Diagram
22.8.2.1
Bus Timing
The Timing Register (TR) is used to control the timing of bus signals driven by the TWIS. TR
describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling
can be selected through TR.EXP.
describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling
can be selected through TR.EXP.
TR has the following fields:
TLOWS: Prescaled clock cycles used to time SMBUS timeout T
LOW:SEXT
.
TWD
TWCK
Start
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM
I²C RTC
I²C LCD
Controller
Slave 1
Slave 2
Slave 3
VDD
I²C Temp.
Sensor
Slave 4
Rp: Pull up value as given by the I²C Standard
Rp
Rp
f
PRESCALED
f
CLK_TWIS
2
EXP
1
+
(
)
-------------------------
=