Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트
제품 코드
AT32UC3A3-XPLD
511
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-3. SSC Functional Block Diagram
24.7.1
Clock Management
The transmitter clock can be generated by:
• an external clock received on the TX_CLOCK pin
• the receiver clock
• the internal clock divider
The receiver clock can be generated by:
• an external clock received on the RX_CLOCK pin
• the transmitter clock
• the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TX_CLOCK pin, and
the receiver block can generate an external clock on the RX_CLOCK pin.
the receiver block can generate an external clock on the RX_CLOCK pin.
This allows the SSC to support many Master and Slave Mode data transfers.
Clock
Divider
User
Interface
Peripheral
Bus
CLK_SSC
Interrupt Control
Start
Selector
Receive Shift Register
Receive Holding
Register
Receive Sync
Holding Register
DMA
Interrupt Controller
RX_FRAME_SYNC
RX_DATA
RX_CLOCK
Frame Sync
Controller
Clock Output
Controller
Receive Clock
Controller
Transmit Holding
Register
Transmit Sync
Holding Register
Transmit Shift Register
Frame Sync
Controller
Clock Output
Controller
Transmit Clock
Controller
Start
Selector
TX_FRAME_SYNC
RX_FRAME_SYNC
TX_CLOCK Input
Transmitter
TX_DMA
Load Shift
RX clock
TX clock
TX_CLOCK
TX_FRAME_SYNC
TX_DATA
Receiver
RX clock
RX_CLOCK
Input
TX clock
TX_FRAME_SYNC
RX_FRAME_SYNC
RX_DMA
Load Shift