Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트
제품 코드
AT32UC3A3-XPLD
519
32072H–AVR32–10/2012
AT32UC3A3
and Transmit Sync bits in the SR register (SR.RXSYN and SR.TXSYN) on frame synchro edge
detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC).
detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC).
24.7.6
Receive Compare Modes
Figure 24-12. Receive Compare Modes
24.7.6.1
Compare functions
Compare 0 can be one start event of the receiver. In this case, the receiver compares at each
new sample the last {RFMR.FSLENHI, RFMR.FSLEN} bits received to the {RFMR.FSLENHI,
RFMR.FSLEN} lower bits of the data contained in the Receive Compare 0 Register (RC0R).
When this start event is selected, the user can program the receiver to start a new data transfer
either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This
selection is done with the Receive Stop Selection bit in the RCMR register (RCMR.STOP).
new sample the last {RFMR.FSLENHI, RFMR.FSLEN} bits received to the {RFMR.FSLENHI,
RFMR.FSLEN} lower bits of the data contained in the Receive Compare 0 Register (RC0R).
When this start event is selected, the user can program the receiver to start a new data transfer
either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This
selection is done with the Receive Stop Selection bit in the RCMR register (RCMR.STOP).
24.7.7
Data Framing Format
The data framing format of both the transmitter and the receiver are programmable through the
TFMR, TCMR, RFMR, and RCMR registers. In either case, the user can independently select:
TFMR, TCMR, RFMR, and RCMR registers. In either case, the user can independently select:
• the event that starts the data transfer (RCMR.START and TCMR.START)
• the delay in number of bit periods between the start event and the first data bit
(RCMR.STTDLY and TCMR.STTDLY)
• the length of the data (RFMR.DATLEN and TFMR.DATLEN)
• the number of data to be transferred for each start event (RFMR.DATNB and TFMR.DATLEN)
• the length of synchronization transferred for each start event (RFMR.FSLENHI,
RFMR.FSLEN, TFMR.FSLENHI, and TFMR.FSLEN)
• the bit sense: most or lowest significant bit first (RFMR.MSBF and TFMR.MSBF)
Additionally, the transmitter can be used to transfer synchronization and select the level driven
on the TX_DATA pin while not in data transfer operation. This is done respectively by writing to
the Frame Sync Data Enable and the Data Default Value bits in the TFMR register
(TFMR.FSDEN and TFMR.DATDEF).
on the TX_DATA pin while not in data transfer operation. This is done respectively by writing to
the Frame Sync Data Enable and the Data Default Value bits in the TFMR register
(TFMR.FSDEN and TFMR.DATDEF).
RX_DATA
(Input)
RX_CLOCK
CMP0
CMP1
CMP2
CMP3
Start
{FSLENHI,FSLEN}
Up to 256 Bits
(4 in This Example)
STTDLY
Ignored
DATLEN
B2
B0
B1
Table 24-3.
Data Framing Format Registers
Transmitter
Receiver
Bit/Field
Length
Comment
TCMR
RCMR
PERIOD
Up to 512
Frame size
TCMR
RCMR
START
Start selection
TCMR
RCMR
STTDLY
Up to 255
Size of transmit start delay