Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트

32072H–AVR32–10/2012

Moreover, the pad goes to the Idle state if the macro is disabled or if the DETACH bit is written to
one. It returns to the Active state when USBE is written to one and DETACH is written to zero.

The USB connection is detected from the USB_VBUS pad. 

 shows the

architecture of the plug-in detector.

Figure 27-10. Plug-In Detection Input Block Diagram

The control logic of the USB_VBUS pad outputs two signals:

• The Session_valid signal is high when the voltage on the USB_VBUS pad is higher than or 

equal to 1.4V.

• The Va_Vbus_valid signal is high when the voltage on the USB_VBUS pad is higher than or 

equal to 4.4V.

In device mode, the USBSTA.VBUS bit follows the Session_valid comparator output:

• It is set when the voltage on the USB_VBUS pad is higher than or equal to 1.4V.

• It is cleared when the voltage on the VBUS pad is lower than 1.4V.

In host mode, the USBSTA.VBUS bit follows an hysteresis based on Session_valid and
Va_Vbus_valid:

• It is set when the voltage on the USB_VBUS pad is higher than or equal to 4.4V.

• It is cleared when the voltage on the USB_VBUS pad is lower than 1.4V.

The VBus Transition interrupt (VBUSTI) bit in USBSTA is set on each transition of the USB-
STA.VBUS bit.

The USBSTA.VBUS bit is effective whether the USBB is enabled or not.

 shows how the ID transitions are detected.

VBUSTI

USBSTA

USB_VBUS

VBUS

USBSTA

GND

VDD

Pad Logic

Logic

Session_valid

Va_Vbus_valid

R

PU

R

PD

VBus_pulsing

VBus_discharge