Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트

32072H–AVR32–10/2012

Figure 27-27. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay

Figure 27-28. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay

This error exists only for isochronous IN pipes. It set the CRC Error Interrupt (CRCERRI) bit,
what triggers a PnINT interrupt if then the CRC Error Interrupt Enable (CRCERRE) bit in
UPCONn is one.

A CRC error can occur during IN stage if the USBB detects a corrupted received packet. The IN
packet is stored in the bank as if no CRC error had occurred (RXINI is set).

See the structure of the USB host interrupt system on 

There are two kinds of host interrupts: processing, i.e. their generation is part of the normal pro-
cessing, and exception, i.e. errors (not related to CPU exceptions).

The processing host global interrupts are:

• The Device Connection Interrupt (DCONNI)

• The Device Disconnection Interrupt (DDISCI)

OUT

DATA

(bank 0)

ACK

TXOUTI

FIFOCON

write data to CPU

BANK 0

SW

SW

SW

SW

write data to CPU

BANK 1

SW

HW

write data to CPU

BANK0

OUT

DATA

(bank 1)

ACK

OUT

DATA

(bank 0)

ACK

TXOUTI

FIFOCON

write data to CPU

BANK 0

SW

SW

SW

SW

OUT

DATA

(bank 1)

ACK

write data to CPU

BANK 1

SW

HW

write data to CPU

BANK0