Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트

32072H–AVR32–10/2012

UESTAn, n in [0..7]

Read-Only 0x0100

0x0130 + (n * 0x04)

0x00000100

This field is set with the byte count of the FIFO.

For IN endpoints, incremented after each byte written by the software into the endpoint and decremented after each byte sent to 

the host.

For OUT endpoints, incremented after each byte received from the host and decremented after each byte read by the software 

from the endpoint.

This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.

This bit is updated when the ALLOC bit is written to one.

This bit is set if the endpoint n number of banks (EPBK) and size (EPSIZE) are correct compared to the maximal allowed 

number of banks and size for this endpoint and to the maximal FIFO size (i.e. the DPRAM size).

If this bit is cleared, the user shall rewrite correct values to the EPBK and EPSIZE fields in the UECFGn register.

This bit is set after a SETUP packet to indicate that the following packet is an IN packet.

This bit is cleared after a SETUP packet to indicate that the following packet is an OUT packet.

Writing a zero or a one to this bit has no effect.

This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO.

This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO.

This bit is never set if STALLRQ is one or in case of error.

This bit is cleared otherwise.

This bit shall not be used for control endpoints.

31

30

29

28

27

26

25

24

-

BYCT

23

22

21

20

19

18

17

16

BYCT

-

CFGOK

CTRLDIR

RWALL

15

14

13

12

11

10

9

8

CURRBK

NBUSYBK

-

ERRORTRANS

DTSEQ

7

6

5

4

3

2

1

0

SHORT

PACKET

STALLEDI/

CRCERRI

OVERFI

NAKINI/ 

HBISOFLUSHI

NAKOUTI/ 

HBISOINERRI

RXSTPI/

UNDERFI

RXOUTI

TXINI