Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트
제품 코드
AT32UC3A3-XPLD
760
32072H–AVR32–10/2012
AT32UC3A3
Figure 28-7. WAVSEL= 0 With Trigger
28.6.3.3
WAVSEL = 2
When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC,
then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then
incremented and so on. See
then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then
incremented and so on. See
.
It is important to note that CVn can be reset at any time by an external event or a software trig-
ger if both are programmed correctly. See
ger if both are programmed correctly. See
In addition, RC Compare can stop the counter clock (CMRn.CPCSTOP) and/or disable the
counter clock (CMRn.CPCDIS = 1).
counter clock (CMRn.CPCDIS = 1).
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter cleared by trigger