Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트
제품 코드
AT32UC3A3-XPLD
936
32072H–AVR32–10/2012
AT32UC3A3
35.4.3
Block Diagram
Figure 35-4. JTAG and Boundary-scan Access
35.4.4
I/O Lines Description
35.4.5
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
below.
Table 35-6.
I/O Line Description
Pin Name
Pin Description
Type
Active Level
TCK
Test Clock Input. Fully asynchronous to system clock frequency.
Input
TMS
Test Mode Select, sampled on rising TCK.
Input
TDI
Test Data In, sampled on rising TCK.
Input
TDO
Test Data Out, driven on falling TCK.
Output
32-bit AVR device
JTAG data registers
TAP
Controller
Instruction Register
Device Identification
Register
By-pass Register
Reset Register
Service Access Bus
interface
B
ou
nd
ar
y S
can
C
hai
n
P
in
s an
d ana
log b
lock
s
Data register
scan enable
JT
AG
Pi
ns
Boundary scan enable
2nd JTAG
device
JTAG master
TDI
TDO
Part specific registers
...
TDO TDI
TMS
TMS
TCK
TCK
Instruction register
scan enable
SAB
Internal I/O
lines
JTAG
TMS
TDI
TDO
TDI
TDO
TCK