Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 데이터 시트
제품 코드
AT32UC3A3-XPLD
977
32072H–AVR32–10/2012
AT32UC3A3
36.11 EBI Timings
36.11.1
SMC Signals
These timings are given for worst case process, T = 85
⋅
C, VDDIO = 3V and 40 pF load
capacitance.
Note:
1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
Note:
1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.
Table 36-30. SMC Clock Signal
Symbol
Parameter
Max.
Unit
1/(t
CPSMC
)
SMC Controller Clock Frequency
1/(t
cpcpu
)
MHz
Table 36-31. SMC Read Signals with Hold Settings
Symbol
Parameter
Min.
Unit
NRD Controlled (READ_MODE = 1)
SMC
1
Data Setup before NRD High
12
ns
SMC
2
Data Hold after NRD High
0
ns
SMC
3
NRD High to NBS0/A0 Change
nrd hold length * t
CPSMC
- 1.3
ns
SMC
4
NRD High to NBS1 Change
nrd hold length * t
CPSMC
-
1.3
ns
SMC
5
NRD High to NBS2/A1 Change
nrd hold length * t
CPSMC
-
1.3
ns
SMC
7
NRD High to A2 - A23 Change
nrd hold length * t
CPSMC
-
1.3
ns
SMC
8
NRD High to NCS Inactive
(nrd hold length - ncs rd hold length) * t
CPSMC
- 2.3
ns
SMC
9
NRD Pulse Width
nrd pulse length * t
CPSMC
- 1.4
ns
NRD Controlled (READ_MODE = 0)
SMC
10
Data Setup before NCS High
11.5
ns
SMC
11
Data Hold after NCS High
0
ns
SMC
12
NCS High to NBS0/A0 Change
ncs rd hold length * t
CPSMC
- 2.3
ns
SMC
13
NCS High to NBS0/A0 Change
ncs rd hold length * t
CPSMC
-
2.3
ns
SMC
14
NCS High to NBS2/A1 Change
ncs rd hold length * t
CPSMC
-
2.3
ns
SMC
16
NCS High to A2 - A23 Change
ncs rd hold length * t
CPSMC
-
4
ns
SMC
17
NCS High to NRD Inactive
ncs rd hold length - nrd hold length)* t
CPSMC
- 1.3
ns
SMC
18
NCS Pulse Width
ncs rd pulse length * t
CPSMC
- 3.6
ns