Linear Technology LTC2635-HMI12: 12-Bit Quad I²C DAC, req DC590 DC1593A-D DC1593A-D 데이터 시트
제품 코드
DC1593A-D
LTC2635
2635fb
pin Functions
V
CC
(Pin 1/Pin 16): Supply Voltage Input. 2.7V ≤ V
CC
≤
5.5V (LTC2635-L) or 4.5V ≤ V
CC
≤ 5.5V (LTC2635-H).
Bypass to GND with a 0.1µF capacitor.
V
V
OUTA
to V
OUTD
(Pins 2, 3, 8, 9/Pins 1, 2, 11, 12): DAC
Analog Voltage Outputs.
LDAC (Pin 3, QFN Only): Asynchronous DAC Update. A
LDAC (Pin 3, QFN Only): Asynchronous DAC Update. A
falling edge on this input after four bytes (slave address
byte plus three data bytes) have been written into the part
immediately updates the DAC registers with the contents
of the input registers (similar to a software update). A
low on this input without a complete 32-bit (four bytes
including the slave address) data write transfer to the part
does not update the DAC output. A low on the LDAC pin
powers up the DACs. A software power down command
is ignored if LDAC is low.
CA0 (Pin 4/Pin 4): Chip Address Bit 0. Tie this pin to V
CA0 (Pin 4/Pin 4): Chip Address Bit 0. Tie this pin to V
CC
,
GND or leave it floating to select an I
2
C slave address for
the part (see Tables 1 and 2).
SCL (Pin 5/Pin 5): Serial Clock Input Pin. Data is shifted
SCL (Pin 5/Pin 5): Serial Clock Input Pin. Data is shifted
into the SDA pin at the rising edges of the clock. This
high-impedance pin requires a pull-up resistor or current
source to V
CC
.
SDA (Pin 6/Pin 8): Serial Data Bidirectional Pin. Data is
shifted into the SDA pin and acknowledged by the SDA
pin. This pin is high impedance while data is shifted in.
Open drain N-channel output during acknowledgment. SDA
requires a pull-up resistor or current source to V
CC
.
REF (Pin 7/Pin 10): Reference Voltage Input or Output.
When External Reference mode is selected, REF is an
input (1V ≤ V
REF
≤ V
CC
) where the voltage supplied sets
the full-scale DAC output voltage. When Internal Reference
is selected, the 10ppm/°C 1.25V (LTC2635-L) or 2.048V
(LTC2635-H) internal reference (half full-scale) is available
at the pin. This output may be bypassed to GND with up
to 10µF, and must be buffered when driving an external
DC load current.
DNC (Pins 6, 15, QFN Only): Do Not Connect These
DNC (Pins 6, 15, QFN Only): Do Not Connect These
Pins.
CA2 (Pin 7, QFN Only): Chip Address Bit 2. Tie this pin to
CA2 (Pin 7, QFN Only): Chip Address Bit 2. Tie this pin to
V
CC
, GND or leave it floating to select an I
2
C slave address
for the part (see Table 1).
CA1 (Pin 9, QFN Only): Chip Address Bit 1. Tie this pin to
CA1 (Pin 9, QFN Only): Chip Address Bit 1. Tie this pin to
V
CC
, GND or leave it floating to select an I
2
C slave address
for the part (see Table 1).
GND (Pin 10, Exposed Pad Pin 11/Pin 14, Exposed Pad
GND (Pin 10, Exposed Pad Pin 11/Pin 14, Exposed Pad
Pin 17): Ground. Must be soldered to PCB ground.
REFLO (Pin 13, QFN Only): Reference Low Pin. The volt-
REFLO (Pin 13, QFN Only): Reference Low Pin. The volt-
age at this pin sets the zero-scale voltage of all DACs. This
pin must be tied to GND.
(MSOP/QFN)