Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 데이터 시트
제품 코드
ATEVK1105
413
AT32UC3A
28.5.2
Software Interface
The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller
allows mapping different memory types according to the values set in the SDRAMC configura-
tion register.
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user.
to
illustrate the SDRAM device memory mapping seen by the
user in correlation with the device structure. Various configurations are illustrated.
28.5.2.1
32-bit Memory Data Bus Width
Notes: 1. M[1:0] is the byte address inside a 32-bit word.
2. Bk[1] = BA1, Bk[0] = BA0.
Table 28-2.
SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
2
7
7
2
6
6
2
5
5
2
4
4
2
3
3
2
2
2
2
1
1
2
0
0
1
9
9
1
8
8
1
7
7
1
6
6
1
5
5
1
4
4
1
3
3
1
2
2
1
1
1
1
0
0
9
8
7
6
5
4
3
2
1
0
Bk[1:0]
Row[10:0]
Column[7:0]
M[1:0]
Bk[1:0]
Row[10:0]
Column[8:0]
M[1:0]
Bk[1:0]
Row[10:0]
Column[9:0]
M[1:0]
Bk[1:0]
Row[10:0]
Column[10:0]
M[1:0]
Table 28-3.
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
2
7
7
2
6
6
2
5
5
2
4
4
2
3
3
2
2
2
2
1
1
2
0
0
1
9
9
1
8
8
1
7
7
1
6
6
1
5
5
1
4
4
1
3
3
1
2
2
1
1
1
1
0
0
9
8
7
6
5
4
3
2
1
0
Bk[1:0]
Row[11:0]
Column[7:0]
M[1:0]
Bk[1:0]
Row[11:0]
Column[8:0]
M[1:0]
Bk[1:0]
Row[11:0]
Column[9:0]
M[1:0]
Bk[1:0]
Row[11:0]
Column[10:0]
M[1:0]
Table 28-4.
SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
2
7
7
2
6
6
2
5
5
2
4
4
2
3
3
2
2
2
2
1
1
2
0
0
1
9
9
1
8
8
1
7
7
1
6
6
1
5
5
1
4
4
1
3
3
1
2
2
1
1
1
1
0
0
9
8
7
6
5
4
3
2
1
0
Bk[1:0]
Row[12:0]
Column[7:0]
M[1:0]
Bk[1:0]
Row[12:0]
Column[8:0]
M[1:0]
Bk[1:0]
Row[12:0]
Column[9:0]
M[1:0]
Bk[1:0]
Row[12:0]
Column[10:0]
M[1:0]
32058K
AVR32-01/12