Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK 데이터 시트

42023E–SAM–07/2013

Figure 27-7. Master Write with Multiple Data Bytes

A START condition is transmitted and master receiver mode is initiated when the bus is free and
CMDR has been written with START=1 and READ=1. START and SADR+R will then be trans-
mitted. During the address acknowledge clock pulse (9th pulse), the master releases the data
line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master
polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in
the Status Register if no slave acknowledges the address. 

After the address phase, the following is repeated:

while (NBYTES>0)

1.

Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state 
of RHR. Software or the Peripheral DMA Controller must read any data byte present in 
RHR.

2.

Release TWCK generating a clock that the slave uses to transmit a data byte.

3.

Place the received data byte in RHR, set RXRDY.

4.

If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK.

5.

Decrement NBYTES

6.

If (NBYTES==0) and STOP=1, transmit STOP condition.

Writing CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data
bytes, ie START, DADR+R, STOP

The TWI transfers require the master to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the mas-
ter to pull it down in order to generate the acknowledge. All data bytes except the last are
acknowledged by the master. Not acknowledging the last byte informs the slave that the transfer
is finished.

RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.

TWD

SR.IDLE

TXRDY

Write THR 

(DATAn)

NBYTES set to n

STOP sent automatically

(ACK received and NBYTES=0)

S

DADR

W

A

DATAn

A

DATAn+5

A

A

DATAn+m

P

Write THR 

(DATAn+1)

Write THR 

(DATAn+m)

Last data sent