Linear Technology LTC2174-12 12-Bit, 105Msps, 1.8V Quad Serial ADC, 5MHz DC1525A-H 데이터 시트

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dc1525af

DEMO MANUAL DC1525A

Demonstration circuit 1525A is easy to set up to evaluate 
the performance of the LTC2175 A/D converters. Refer to 
Figure 1 for proper measurement equipment setup and 
follow this procedure.

If a DC1371 QuikEval™ II Data Acquisition and Collection 
System was supplied with the DC1525A demonstration 
circuit, follow the DC1371 Quick Start Guide to install the 
required software and for connecting the DC1371 to the 
DC1525A and to a PC.

The DC1525A demonstration circuit board should have 
the following jumper settings as default positions: (as 
per Figure 1).

J13:  PAR/SER: Selects Parallel or Serial programming 
mode. (Default – Serial)

Optional Jumpers:

J8:  Term: Enables/Disable optional output termination. 
(Default – Removed)

J5:  ILVDS: Selects either 1.75mA or 3.5mA of output 
current for the LVDS drivers. (Default – Removed)

J14:  LANE: Selects either 1 lane or 2 lane output modes 
(Default – Removed) NOTE: The DC1371 does not support 
1 lane operation.

J15: SHDN: Enables and disables the LTC2175. (De-
fault – Removed)

J2:  WP: Enable/Disables write protect for the EEPROM. 
(Default – Removed)

Note: optional jumper should be left open to ensure proper 
serial configuration.

The DC1371 is used to acquire data from the DC1525A, 
the DC1371 must FIRST be connected to a powered USB 
port and have equal to 5V applied power BEFORE applying 
3.6V to 6V across the pins marked V

+

 and GND on the 

DC1525A. DC1525A requires 3.6V for proper operation.

Regulators on the board produce the voltages required for 
the ADC. The DC1525A demonstration circuit requires up 
to 500mA depending on the sampling rate and the A/D 
converter supplied.

The DC1525A should not be removed, or connected to 
the DC1371 while power is applied.

Supply Voltage: DC1525A

Depending on Sampling Rate and the A/D Converter Provided, 
this Supply Must Provide Up to 500mA.

Optimized for 3V
[3V 

↔ 6.0V Min/Max]

Analog Input Range

Depending on SENSE Pin Voltage

1V

P-P

 to 2V

P-P

Logic Input Voltages

Minimum Logic High

1.3V

Maximum Logic Low

0.6V

Logic Output Voltages (Differential)

Nominal Logic Levels (100Ω Load, 3.5mA Mode)

350mV/1.25V Common Mode

Minimum Logic Levels (100Ω Load, 3.5mA Mode)

247mV/1.25V Common Mode

Sampling Frequency (Convert Clock Frequency)

See Table 1

Encode Clock Level

Single-ended Encode Mode (ENC

–

 Tied to GND)

0V to 3.6V

Encode Clock Level

Differential Encode Mode (ENC

–

 Not Tied to GND)

0.2V to 3.6V

Resolution

See Table 1

Input Frequency Range

See Table 1

SFDR

See Applicable Data Sheet

SNR

See Applicable Data Sheet