Linear Technology LTM4613EV Demo Board: Ultralow EMI, 36V, 8A Step-down µModule Regulator DC1743A DC1743A 데이터 시트
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제품 코드
DC1743A
LTM4613
11
4613f
APPLICATIONS INFORMATION
Figure 2. Operating Frequency vs Output Voltage
Operating Frequency
The operating frequency of the LTM4613 is optimized to
The operating frequency of the LTM4613 is optimized to
achieve the compact package size and the minimum
output ripple voltage while still keeping high efficiency.
As shown in Figure 2, the frequency is linearly increased
with larger output voltages to keep the low output cur-
rent ripple. Figure 3 shows the inductor current ripple ∆I
with different output voltages. In most applications, no
additional frequency adjusting is required.
If lower output ripple is required, the operating frequency
If lower output ripple is required, the operating frequency
f can be increased by adding a resistor R
fSET
between f
SET
pin and SGND, as shown in Figure 19.
f
=
V
OUT
1.5 • 10
−10
R
fSET
|| 133k
(
)
Figure 3. Pk-Pk Inductor Current Ripple vs Output Voltage
Table 1. R
FB
Standard 1% Resistor Values vs V
OUT
V
OUT
(V)
3.3
5
6
8
10
12
14
15
R
FB
(kΩ) 22.1
13.7
11
8.06
6.34
5.23
4.42
4.12
The MPGM pin programs a current that when multiplied
by an internal 10k resistor sets up the 0.6V reference ±
offset for margining. A 1.18V reference divided by the
R
PGM
resistor on the MPGM pin programs the current.
Calculate V
OUT(MARGIN)
:
V
OUT(MARGIN)
=
%V
OUT
100
• V
OUT
Where %V
OUT
is the percentage of V
OUT
to be margined,
and V
OUT(MARGIN)
is the margin quantity in volts:
R
PGM
=
V
OUT
0.6V
•
1.18V
V
OUT(MARGIN)
• 10k
Where R
PGM
is the resistor value to place on the MPGM
pin to ground.
The output margining will be ± margining of the value.
The output margining will be ± margining of the value.
This is controlled by the MARG0 and MARG1 pins. See
the truth table below:
MARG1
MARG0
MODE
LOW
LOW
NO MARGIN
LOW
HIGH
MARGIN UP
HIGH
LOW
MARGIN DOWN
HIGH
HIGH
NO MARGIN
Parallel Operation
The LTM4613 device is an inherently current mode con-
The LTM4613 device is an inherently current mode con-
trolled device. This allows the paralleled modules to have
very good current sharing and balanced thermal on the
design. Figure 21 shows a schematic of the parallel design.
The voltage feedback equation changes with the variable
N as modules are paralleled. The equation:
R
FB
=
100k
N
V
OUT
0.6V
− 1
where N is the number of paralleled modules.
OUTPUT VOLTAGE (V)
2
4
0
FREQUENCY (kHz)
400
1000
6
10
12
4613 F02
200
800
600
8
14
16
OUTPUT VOLTAGE (V)
2
0
PK-PK INDUCTOR CURRENT RIPPLE (A)
1
3
4
5
10
9
4613 F03
2
6
4
12
14
8
16
6
7
8
V
IN
= 16V
V
IN
= 24V
V
IN
= 28V
V
IN
= 36V