Nxp Semiconductors OM11043 데이터 시트
LPC1769_68_67_66_65_64_63
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Product data sheet
Rev. 9.5 — 24 June 2014
32 of 89
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.20 I
2
S-bus serial I/O controllers
Remark: The I
2
S-bus interface is available on parts LPC1769/68/67/66/65/63. See
The I
2
S-bus provides a standard communication interface for digital audio applications.
The I
2
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I
2
S-bus connection has one master, which is
always the master, and one slave. The I
2
S-bus interface provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.
8.20.1 Features
•
The interface has separate input/output channels each of which can operate in master
or slave mode.
or slave mode.
•
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
•
Mono and stereo audio data supported.
•
The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,
96) kHz.
96) kHz.
•
Support for an audio master clock.
•
Configurable word select period in master mode (separately for I
2
S-bus input and
output).
•
Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
•
Generates interrupt requests when buffer levels cross a programmable boundary.
•
Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
to the GPDMA block.
•
Controls include reset, stop and mute options separately for I
2
S-bus input and I
2
S-bus
output.
8.21 General purpose 32-bit timers/external event counters
The LPC17xx include four 32-bit timer/counters. The timer/counter is designed to count
cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts, generate timed DMA requests, or perform other actions at specified
timer values, based on four match registers. Each timer/counter also includes two capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts, generate timed DMA requests, or perform other actions at specified
timer values, based on four match registers. Each timer/counter also includes two capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
8.21.1 Features
•
A 32-bit timer/counter with a programmable 32-bit prescaler.
•
Counter or timer operation.
•
Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
when an input signal transitions. A capture event may also generate an interrupt.
•
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.