STMicroelectronics LED815 Evaluation Boards EVALHVLED815W15 EVALHVLED815W15 데이터 시트
제품 코드
EVALHVLED815W15
Device description
HVLED815PF
30/36
Doc ID 023409 Rev 4
Equation 24
where V
CLED
is internally defined (0.2 V typical - see
System design tips
Starting from the estimated value using the previous formulas, further fine-tuning on the real
led driver board could be necessary and it can be easily done considering that:
led driver board could be necessary and it can be easily done considering that:
–
Decreasing/increasing the R
PF
resistor value, the power factor effect
increase/decrease
–
Decreasing/increasing the R
OS
resistor value, the line-regulation effect
increase/decrease
–
Decreasing/increasing the R
OS
resistor value, the R
A
+R
B
resistors value should
be increase/decrease to keep the desiderated voltage across the C
OS
capacitor
(Equation
).
–
Decreasing/increasing the R
SENSE
resistor value the average output current
increase/decrease (Equation
4.12 Layout
recommendations
A proper printed circuit board layout is essential for correct operation of any switch-mode
converter and this is true for the HVLED815PF as well. Careful component placing, correct
traces routing, appropriate traces widths and compliance with isolation distances are the
major issues.
converter and this is true for the HVLED815PF as well. Careful component placing, correct
traces routing, appropriate traces widths and compliance with isolation distances are the
major issues.
In particular:
●
Current sense resistor (R
SENSE
) should be connected as close as possible to the
SOURCE pin, maintaining the trace for the GND as short as possible.
●
Resistor connected on CS pin (R
OS
, R
PF
, R
1
) should be connected as close as possible
to the pin.
●
Compensation network (R
COMP
, C
COMP
) should be connected as close as possible to
the COMP pin, maintaining the trace for the GND as short as possible.
●
Signal ground should be routed separately from power ground, as well from the sense
resistor trace.
resistor trace.
●
DMG partition resistors (R
DMG
, R
FB
) should be connected as close as possible to the
DMG pin, minimizing the equivalent parasitic capacitor on DMG pin.